1 Field of Invention
In general terms, the present invention relates to an apparatus for conveying a particular image of a memory array of a data processing system to a microprogrammer for writing of microprograms for implementating a processor task of the system, wherein the image which contains aligned bits and is of variable length, without any regard to problems respecting data framing and response periods of the memory array. More specifically, the present invention relates to an apparatus for managing data transfers between a memory array and different processing units of the system while a task is implemented by a processor of the system, while minimizing the number of memory accesses.
2. Description of the Prior Art
As a rule, the data to be read or written in a memory array of a digital data processing system during the implementation of a task by a processor of the system, essentially comprise chains of octets having optional length. The initial octet is located at an optional address with progression of the addresses towards the right or left. The data transfers relating to instructions, as well as to information, are all under the control of a set of pre-recorded microprograms. These microprograms are called up selectively and performed during the implementation of a task.
A microprogrammer who writes these microprograms should make allowance for the structure of the data, for the data recording mode in the memory array, for the data length and the data framing. Furthermore, the data relating to instructions and to information items are transferred as and when required.
One of the objects of the invention is to enable these microprograms to be more simply written by optimum freeing of the microprogrammer from the restrictions imposed by the indentifications of the data which are to be processed. In these circumstances, the restrictions eliminated at the microprogram writing stage are taken into account and managed automatically by the system in accordance with the invention.
Another object of the invention is to control the data transfers at the instruction stage as well as at the information item stage in such a manner as to limit memory accesses as much as possible and thereby save time in the implementation of a task. This management of the transfers is provided automatically by the system in accordance with the invention.
Another object of the invention is to gain freedom from the constrictions imposed by the variable response periods of the memory array, which response periods depend on the configuration of the system.